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the writes of Ti and Tj do not overlap Since the writes of Ti do not affect the read of Tj , and since Tj cannot affect the read of Ti , the serializability order is indeed maintained As an illustration, consider again transactions T14 and T15 Suppose that TS(T14 ) < TS(T15 ) Then, the validation phase succeeds in the schedule 5 in Figure 1615 Note that the writes to the actual variables are performed only after the validation phase of T15 Thus, T14 reads the old values of B and A, and this schedule is serializable The validation scheme automatically guards against cascading rollbacks, since the actual writes take place only after the transaction issuing the write has committed However, there is a possibility of starvation of long transactions, due to a sequence of con icting short transactions that cause repeated restarts of the long transaction To avoid starvation, con icting transactions must be temporarily blocked, to enable the long transaction to nish This validation scheme is called the optimistic concurrency control scheme since transactions execute optimistically, assuming they will be able to nish execution and validate at the end In contrast, locking and timestamp ordering are pessimistic in that they force a wait or a rollback whenever a con ict is detected, even though there is a chance that the schedule may be con ict serializable

In the concurrency-control schemes described thus far, we have used each individual data item as the unit on which synchronization is performed There are circumstances, however, where it would be advantageous to group several data items, and to treat them as one individual synchronization unit For example, if a transaction Ti needs to access the entire database, and a locking protocol is used, then Ti must lock each item in the database Clearly, executing these locks is time consuming It would be better if Ti could issue a single lock request to lock the

Although we know V5 = 7 V this equation leaves us with two unknowns , With one equation and two unknowns we need more information to solve the problem Some extra information comes in the form of Ohm s law The same current I3 ows through the 10 and 3 resistors Hence V10 = 10I3 and V3 = 3I3 and we can write (212) as 7 + 10I3 + 20 + 3I3 = 0 I3 = 1 A Knowing two of the currents, we can solve for the other current by considering KCL at the top-center node We take + for currents entering the node and for currents leaving the node This gives I1 I2 I3 = 0 Therefore we have I1 = I2 + I3 = 14 1 = 04 A Now we apply Ohm s law again to get the voltages across each of the resistors V10 = 10I3 = 10 ( 1) = 10 V V3 = 3I3 = 3 ( 1) = 3 V Notice the minus signs These tell us that the actual voltages have the polarity opposite to that indicated in Fig 2-8 EXAMPLE 2-6 Let s consider a simple abstract model of a toaster Our model will consist of the wall outlet, an electric chord, a switch, and a heating element The wall outlet

FIGURE 3-2

The McGraw Hill Companies, 2001

16

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1 A capacitor with C = 1 F is in an RC circuit with a 100 resistor What is the time constant 2 How long does it take for the voltage in the circuit described in Problem 1 to decay to zero 3 A current increases uniformly from 10 to 100 mA in 20 ms in a coil This induces a voltage of 2 V What is the inductance of the coil 4 Consider an RL circuit with R = 10 , L = 2 H in series with a voltage source with v(t) = 24e t Find the total solution Assume the initial current is zero 5 Consider an RL circuit with R = 8 , L = 4 H in series with a voltage source with v(t) = 4 cos 10t Find the total solution Assume the initial current is zero 6 Consider an RL circuit with R = 8 , L = 4 H in series with a voltage source with v(t) = 4t Find the total solution Assume the initial current is i(t) = 2 A 7 The equation obeyed by the current in a parallel RLC circuit with zero input is LC d 2i L di +i =0 + 2 dt R dt