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The nal result of these swaps, schedule 6 of Figure 159, is a serial schedule Thus, we have shown that schedule 3 is equivalent to a serial schedule This equivalence implies that, regardless of the initial system state, schedule 3 will produce the same nal state as will some serial schedule If a schedule S can be transformed into a schedule S by a series of swaps of noncon icting instructions, we say that S and S are con ict equivalent In our previous examples, schedule 1 is not con ict equivalent to schedule 2 However, schedule 1 is con ict equivalent to schedule 3, because the read(B) and write(B) instruction of T1 can be swapped with the read(A) and write(A) instruction of T2 The concept of con ict equivalence leads to the concept of con ict serializability We say that a schedule S is con ict serializable if it is con ict equivalent to a serial schedule Thus, schedule 3 is con ict serializable, since it is con ict equivalent to the serial schedule 1 Finally, consider schedule 7 of Figure 1510; it consists of only the signi cant operations (that is, the read and write) of transactions T3 and T4 This schedule is not con ict serializable, since it is not equivalent to either the serial schedule <T3 ,T4 > or the serial schedule <T4 ,T3 > It is possible to have two schedules that produce the same outcome, but that are not con ict equivalent For example, consider transaction T5 , which transfers $10

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T1 read(A) write(A) read(B) write(B)

FIGURE 2-19

read(A) write(A) read(B) write(B) Figure 159 Schedule 6 a serial schedule that is equivalent to schedule 3

The McGraw Hill Companies, 2001

Finding the zero-input response of an RL circuit proceeds in an fashion analogous to method used to nd the zero-input response for an RC circuit However, this time we take the initial condition to be the initial current rather than the initial voltage The circuit we wish to solve is shown in Fig 6-12 Using v=L for the inductor and v = Ri For the resistor, we apply KVL to a loop about the circuit shown in Fig 6-12 This gives the differential equation L Hence di R = dt i L Integrating gives us the transient current in the RL circuit We nd it to be i(t) = i(0)e (R/L)t (624) di + Ri = 0 dt di dt

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T4 write(Q)

CHAPTER 2:

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from account B to account A Let schedule 8 be as de ned in Figure 1511 We claim that schedule 8 is not con ict equivalent to the serial schedule <T1 ,T5 >, since, in schedule 8, the write(B) instruction of T5 con icts with the read(B) instruction of T1 Thus, we cannot move all the instructions of T1 before those of T5 by swapping consecutive noncon icting instructions However, the nal values of accounts A and B after the execution of either schedule 8 or the serial schedule <T1 ,T5 > are the same $960 and $2040, respectively We can see from this example that there are less stringent de nitions of schedule equivalence than con ict equivalence For the system to determine that schedule 8 produces the same outcome as the serial schedule <T1 ,T5 >, it must analyze the computation performed by T1 and T5 , rather than just the read and write operations In general, such analysis is hard to implement and is computationally expensive However, there are other de nitions of schedule equivalence based purely on the read and write operations We will consider one such de nition in the next section

where i(0) is the initial current For an RL circuit, the time constant is given by = L/R (625)

In this section, we consider a form of equivalence that is less stringent than con ict equivalence, but that, like con ict equivalence, is based on only the read and write operations of transactions

T1 read(A) A := A 50 write(A)

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read(B) B := B 10 write(B) read(B) B := B + 50 write(B) read(A) A := A + 10 write(A) Figure 1511 Schedule 8

The McGraw Hill Companies, 2001

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